Maintaining Power Integrity

Delivering clean power to the chips in the boards is a real challenge with the evolution of technology. Chips designed these days are power hungry and draw huge current typically several amps. And more interesting thing in this is the operating voltages of the digital cores have reduced by many fold as the devices shrunk. Typical digital core of this era has more transistors than the previous decade chips and are smaller and faster than the latter. Because of the shrink in device size and operating voltages the target impedance of the power distribution network falls greatly. This needs high impedance in DC and zero impedance in the other frequencies. But constructing zero impedance PDN is impossible and the impedance of the PDN must be limited to target impedance. The typical power distribution network to deliver clean power to devices connected to it, must have the impedance equal to the target impedance. The power pins of the chips must see target impedance at the local power bus.

ZTarget = ∆V/I

Where ∆V is the maximum allowed ripple voltage in the PDN and I is the current drawn by the devices. Target impedance must be calculated for all the frequencies within the maximum frequency limit. The PDN of the system is designed for this target impedance. Normally ∆V is normally expressed as R x V, where R is the maximum allowed ripple %. If in the datasheet of a device displays a tolerance of +/- 10% of 3.3V operating voltage and draws 1 A in 1ns the target impedance is calculated as,
Ztarget = 10% x 3.3 V / 1A = 0.33V / 1 A = 0.33Ω
Here the device draws a current of 1A to in 1ns that means the bandwidth is calculated by,

F = 0.35 / Tr = 0.35 / 1ns = 350 MHz

The impedance of the PDN must equal 0.33Ω in this case for all frequencies less than 350MHz to deliver a sufficiently clean power to the devices connected to it.